The field of the invention is that of DRAM arrays on SOI wafers, in particular for ultra-thin insulating layers.
In SOI circuits having trench capacitor DRAM arrays, the capacitor is connected to the pass transistor through a buried strap that makes electrical contact with the device layer at a vertical surface abutting the capacitor trench.
The conventional DRAM layout in which cells are staggered so that xe2x80x9cpassing wordlinesxe2x80x9d pass over trench capacitors in adjacent rows of the array works when the thickness of the insulator between the passing wordline and the capacitor is great enough to suppress coupling (including shorts), but the decreasing thickness of the device layer has caused the thickness of the trench top oxide (TTO) to decrease correspondingly, so that it is no longer possible to retain the passing wordline layout with conventional manufacturing tolerances.
Accordingly, in the prior art, the cell layout for SOI circuits with thin device layers must be changed, increasing the size of the DRAM cell.
The art would benefit from a DRAM cell structure that retains the advantages of a thin device layer while still permitting the passing wordlines to pass over the trenches in adjacent rows.
The invention relates to a DRAM cell structure for SOI technology in which the buried strap makes contact with the bottom of the device layer.
A feature of the invention is the recess of the trench center electrode to a depth within a manufacturing tolerance of the bottom of the device layer.
Another feature of the invention is an isotropic etch to expand the trench laterally to undercut the device layer with an expanded aperture.
Another feature of the invention is filling the expanded aperture with a conformal conductor.
Yet another feature of the invention is coating the surfaces of the expanded aperture with a conductive material before the filling step.